職缺說明

IR: • Power mesh/power density flow development and related flow development and enhancement. • Provide power plan result for PR team. • Chip IR signoff : provide the result and solution to APR • Chip level PEM/SEM simulation and fixing plan providing. • SIR/DIR/PEM/SEM result data review and verification. PD: • Work on 22nm~6nm design implementation, methodology, and sign-off • Perform floorplan, power plan, place and route, timing closure, ECO • Hands on partition APR physical design from netlist to DRC/LVS tapeout • Familiar with Cadence Innovus & Synopsys ICC/ICC2 experience is better.

職缺說明

1. 通訊演算法設計 2. 算法性能分析評估 3. 算法實作及驗證

職缺說明

Hands-on experience in the design and development of at least one of the following analog circuits: ADC, DAC, PGA, high-speed analog driver, PLL, or SerDes.

職缺說明

1. 射頻電路開發 2. 射頻電路量測與除錯

職缺說明

1. SAR ADC / Current steering DAC/ SDM ADC/ DAC related 2. Analog Baseband related

職缺說明

1. High-Speed Serdes System Design 2. PAM-4 system design 3. SERDES Verification

職缺說明

1.高速驅動器架構設計 -負責PAM4 SERDES發射端驅動器（TX Driver）電路設計，包括差動驅動器(CML/VML) 和 T-coil peaking。 2.信號完整性與等化技術 -進行信號完整性分析，設計預加重、去加重及等化器以提升高速傳輸品質。 3.高速佈局與寄生效應考量 -熟悉高速佈局與寄生效應，與版圖工程師協作優化設計。

職缺說明

1. 光通訊產品相關高速介面數位設計 (112G PAM4 SerDes) 2. 依據系統規格, 執行架構設計以及撰寫硬體描述語言 (RTL) 3. 具有高速介面, 低功耗, 以及D/A混合電路設計經驗者尤佳